The present invention relates to an operation of a non-volatile memory device and, more particularly, to a non-volatile memory device and a method of operating the same, in which a pass voltage is supplied depending on the characteristics of word lines.
Semiconductor memory devices can be classified into volatile memory devices which do not retain data, such as dynamic random access memory (DRAM) and static random access memory (SRAM), and non-volatile memory devices which retain data after the data is input.
Recently, there has been an increasing demand for flash memory into which data can be electrically input or from which data can be electrically erased. Flash memory is a device that can be electrically erased at a high speed without removing its circuits from a board. Flash memory is advantageous in that it has a simple memory cell structure and a low manufacturing cost per unit memory, and does not need a refresh function for retaining data.
Flash memory can be largely classified into the NOR type and the NAND type. The NOR flash memory requires one contact per two cells. It is disadvantageous in terms of higher integration, but is advantageous in terms of higher speed due to a high cell current. The NAND flash memory is disadvantageous in terms of higher speed due to a low cell current, but is advantageous in terms of higher integration since a plurality of cells shares one contact. Thus, NAND flash memory devices have become increasingly popular as next-generation memory devices in line with the rapid increase in the use of digital devices such as MP3 players, digital cameras, mobile devices, and assistant storage devices.
FIG. 1 is a sectional view showing a unit string of a NAND flash memory device.
Referring to FIG. 1, a unit string of a NAND flash device includes memory cells MC0, . . . , MC31. The memory cells are connected in series to constitute one string. Each memory cell has a gate in which a floating gate 110 and a control gate 120 are stacked between a drain select transistor DST for selecting a unit string and a source select transistor SST for selecting a ground.
The string is connected to a bit line BL. A structure in which the string and the bit line are connected is connected in parallel in plural numbers, thereby forming one block. The blocks are arranged symmetrically on the basis of a bit line contact. The select transistors DST, SST and the memory cells MC0, . . . , MC31 are arranged in matrix form of rows and columns. The gates of the drain select transistor DST and the source select transistor SST arranged in the same column are connected to a drain select line DSL and a source selective line SSL, respectively. The gates of the memory cells MC0, . . . , MC31 arranged in the same column are also connected to a plurality of corresponding word lines WL0, . . . , WL31. Further, the drain of the drain select transistor DST is connected to the bit line BL. A common source line CSL is connected to the source of the source select transistor SST.
A program operation of the NAND flash memory device constructed as above is described below.
A selected bit line is applied with a voltage of 0V and a selected word line is applied with a program voltage Vpgm to perform a program operation. Electrons of a channel region are injected into the floating gate by the Fowler-Nordheim (F-N) tunneling mechanism due to a high voltage difference between the channel region and the control gate of a selected memory cell.
The program voltage Vpgm is applied to not only a selected memory cell, but also unselected memory cells arranged in the same word line. Thus, the unselected memory cells connected to the same word line are also programmed. This phenomenon is called program disturbance. To inhibit program disturbance, the source of a drain select transistor DST of a string, including an unselected memory cell connected to a selected word line and a unselected bit line, is discharged to Vcc-Vth (Vcc is a power supply voltage and Vth is the threshold voltage level of the drain select transistor), the selected word line is applied with the program voltage Vpgm, and the unselected word line is applied with the pass voltage Vpass so that a channel voltage Vch of memory cells belonging to the same string is boosted.
In the method of inhibiting unselected memory cells from being programmed by boosting the channel voltage, the degree of boosting can be varied depending on how program cells are arranged near a selected word line and how many memory cells are in a program state. Further, disturbance may be caused since boosting is not sufficient.